1. Field of the Invention
The invention herein relates to the formation of an integrated circuit including a capacitor. More specifically, this invention relates to the formation of a metal-insulator-metal capacitor in an integrated circuit.
2. Description of the Related Art
As integrated circuit (IC) complexity increases, the number of interconnections used in an IC increases accordingly. IC fabrication methods providing layouts multiple metal layer layouts have become popular techniques for accommodating increased number of interconnections in such ICs. Because highly-integrated ICs face difficulties meet the requisite yield and interconnect reliability requirements, newer methods and structures have been developed and applied in the semiconductor fabrication process. Two recently-developed fabrication techniques include the single damascene process and the dual damascene process. Single damascene is an interconnection fabrication process in which grooves are formed in an insulating layer and filled with metal, for example, copper, to form the conductive lines. Dual damascene is a multi-level interconnection process in which conductive via openings are formed in addition to forming the grooves of single damascene. Dual damascene is an improvement over single damascene because it permits the filling of both the conductive grooves and vias with metal at the same time, thereby eliminating process steps. Because a dual damascene structure satisfies the requirement of low resistance and high electromigration, it has been widely used in deep sub-micron VLSI fabrication processes for obtaining an efficient and reliable interconnections. In fabricating very and ultra large scale integration (VLSI and ULSI) circuits with the copper dual damascene process, insulating or dielectric materials are patterned with several thousand openings for the conductive lines and vias, which are filled at the same time with metal, and serve to interconnect the active and/or passive elements of the integrated circuit. However, dual damascene processes using copper metal fill can make device fabrication a daunting task. Copper is a known fast-diffuser and can act to xe2x80x9cpoisonxe2x80x9d a device, creating a failure, once it gets into the active area (i.e., source/drain/gate region of the transistor). This has required the development of new and advanced diffusion barriers to eliminate that threat, as well as different fab layouts to isolate the copper production part of the line from the rest of manufacturing. Metal-insulator-metal (MiM) capacitors are generally used in high-density integrated circuits in a variety of applications. For example, metal-electrode capacitors are widely used in mixed-signal/RF integrated circuits because of their better linearity and higher Q (due to lower electrode resistance) relative to other IC capacitor configurations. Metal-insulator-metal (MiM) capacitors have been commercially available in the standard CMOS mixed-signal process with aluminum interconnects, by adding a few additional steps to the traditional process flow. Present MiM fabrication techniques in dual damascene processes typically involve additional fabrication steps in which extra barrier and dielectric layers needed to form such devices tend to complicate an already difficult and expensive process. What is needed, then, is a MiM capacitor which can be reliably fabricated with fewer process steps using standard materials, preferably eliminating the additional fabrication steps typically associated with creating such devices.
The present invention solve the aforementioned limitations of the prior art by providing an electronic structure, having a first conductive layer provided by a predetermined fabrication process; an etch-stop layer provided by the predetermined fabrication process, the etch-stop layer electrically coupled with the first conductive layer, the etch-stop layer having a preselected dielectric constant and a predetermined geometry; and a second conductive layer, electrically coupled with the etch-stop layer. The preselected dielectric constant is preferred to be above about 4.0, or a relatively xe2x80x9chigh-kxe2x80x9d dielectric value. The etch-stop layer is employed as the capacitor dielectric. The etch-stop layer can be a silicon nitride having a preselected dielectric constant of between about 5.5 and about 9.0. Also, the predetermined fabrication process is desired to be a dual damascene fabrication process, such as a via-first dual damascene process, where at least one of the first and second conductive layers comprises a metal. The electronic structure of the present invention is described for convenience in terms of a metal-insulator-metal capacitor, but the principles herein also can be employed to fabricate a multiplicity of conductor/dielectric structures, including, for example, an antifuse. Furthermore, the structure can be formed from horizontally- and vertically-disposed regions to create the desired aggregate capacitance or other desired electrical characteristics.
The semiconductor device of the present invention employs existing fabrication processes, and in particular the existing etch stop layers, to fabricate the desired devices and structures, thereby minimizing cost and increasing the relative density of desired physical and electrical characteristics. Such a device can include a dielectric matrix with a dielectric constant having a first dielectric value, for example of a low-k (kxe2x89xa6about 4.0) dielectric. Selectively disposed within the dielectric matrix are conductive regions, such as metals or organic conductors, each of the conductive regions having a predetermined shape, and being set apart in at least one of a horizontal direction and a vertical direction, relative to others of the conductive regions. Selected ones of the conductive regions are conductively intercoupled using interconnected metal/via layers. The device also includes etch stop regions selectively disposed within the dielectric matrix. Each of the conductive regions have a predetermined shape, and are set apart in at least one of a horizontal direction and a vertical direction relative to others of the conductive and etch stop regions. Selected ones of the etch stop regions are interposed between respective conductive regions. The etch stop regions have dielectric constants having a second dielectric value, which are effectively greater than the first dielectric values, for example kxe2x89xa75.0. Selected others of the conductive regions, separated by selected ones of the etch stop regions, are capacitively intercoupled by the selected etch stop regions. A first electrode is electrically coupled with a predetermined one of the selected conductively intercoupled conductive regions; and a second electrode is electrically coupled with a predetermined one of the selected others of the conductive regions, separated by selected ones of the etch stop regions, and capacitively intercoupled by the selected etch stop regions. Such a semiconductor device can be readily adapted to a metal-insulator-metal capacitor, and antifuse, or a multiplicity of other conductor/dielectric components and devices.